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Renesas Electronics /R7FA6M3AH /EDMAC0 /EDTRR

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Interpret as EDTRR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)TR

TR=0

Description

EDMAC Transmit Request Register

Fields

TR

Transmit Request

0 (0): no effect.

1 (1): When 1 is written, the EDMAC reads the corresponding descriptor and transmits frames where the TD0.TACT bit is 1. The TR bit becomes 0 after all the valid frames are transmitted.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data